In present day computer circuitry, it is not uncommon to use a wide control store, for example, such as that having a magnitude of 32K words where each word has 200 bits and works in conjunction with a corresponding 200-bit output register (where K equals 1024). The control store will normally hold and carry instruction words to be used by the computer circuitry and the instruction words can be addressed by a sequence of "instruction address data" which will access the relevant instruction words.
When an error detection system is used for wide control stores, the most conventional system is a parity check of the instruction word by adding a parity bit into the instruction word residing in the control store.
These conventional parity error detection methods will cover only the errors caused by memory failures and those which cause the parity of the micro-instruction words to change. However, this type of error detection does not encompass any "instruction address" sequencing errors, since the erroneously accessed instruction would still show up as a valid parity value, since the word accessed was a valid word.
In the typical control store used in electronic circuitry, the instruction sequencing is done by generating the next instruction address through the use of the "next address field" of the present instruction as its "base data", which is under the control of the next address select control field of the present instruction word.
These next address select control fields of the presently existing instruction word can be designated as NAR (next address register) and as NASCR (next address select control register), and as CSR (condition select register).
The NASCR (next address select control register) field controls the selection of the next address from a number of different sources, depending upon which operation-sequence is to be performed.
The next address field, located in the next address register, NAR, may be used as the next instruction address without any changes in the case where the "unconditional" branch operation is being used. This next address may be generated by modifying a portion of the next address field by means of test conditions selected under control of the CSR field in the case of the "conditional" branch operations situation.
The next address (NA) may also be the "subroutine return address" (SRA) in the case of a return from a subroutine.
Or, the next address may be the "initial address" for the new operator, in the case situation where the circuit has finished execution of the current operator and is prepared to enter the new-operator execution routine.
Thus, since there are "multiple sources" of the next instruction address (NA) and since this is a variable and dynamic situation, there is normally no error protection mechanism to handle the situation when an address sequencing error occurs. Additionally it should be noted that the address sequencing error could then result in a very severe problem, such as data corruption, or by the execution of the wrong instruction in this particular case.